1. Field of Application
The present invention relates to a TAD (Time Analog-to-Digital) type of A/D (Analog-to-Digital) converter, in which only digital signal processing is utilized.
2. Description of Related Art
Various TAD A/D converters have been proposed, for example as described in Japanese patent publication No. 5-259907 (referred to in the following as related document 1), in which a pulse delay circuit formed of a plurality of series-connected stages (with each stage made up of a delay unit) delays a pulse signal by an amount that is determined by the voltage level of an (analog) input signal, and in which A/D converted data are outputted as numeric values that express the voltage level of the converter input signal as the number of stages that are traversed by the pulse signal during a predetermined sampling interval. That number of stages can be measured by simultaneously registering (e.g., using latch circuits) the respective output signal values from the delay units at the end of the sampling interval, to thereby detect the position that has been reached by the pulse signal within the series of stages in the pulse delay circuit.
In addition as described in documents such as Japanese patent publication No. 2004-7385 (referred to in the following as related document 2), rather than forming the pulse delay circuit as a linear delay line formed of a set of series-connected stages, the output signal from the final delay unit is transferred to a first input terminal of the first-stage one of a set of series-connected delay units, such as to form a ring-configuration delay line, with a pulse signal being applied to an activation input terminal of the first-stage delay unit at the start of each sampling interval. In each A/D measurement operation, a circulation number counter counts the total number of times the pulse signal circulates around the pulse delay circuit during the sampling interval, while in addition the position reached by the pulse signal within the pulse delay circuit during the sampling interval is also detected, as described for related document 1 above. Each A/D converted output value is obtained as a combination of the count value attained by the circulation number counter (expressing the high-order bits of the converted output value) and a numeric value expressing the position attained by the pulse signal within the pulse delay circuit (expressing the low-order bits of the converted output value).
Another related example is described in Japanese patent publication No. 2004-357030 (referred to in the following as related document 3), whose principles are based on those of the A/D converter of related document 1 above. With that example, instead of detecting the number of delay stages that have been traversed by the pulse signal a single time in each conversion operation at the end point of a single measurement interval, that number is detected n times in succession in each conversion operation, (where n is an integer), at time points that are successively shifted by 1/n times the amount of delay that is currently being applied by each delay unit.
To define each set of successively shifted time points, it is necessary to utilize a clock signal generating circuit which produces a set of sampling clock signals that are respectively shifted in phase from one another by the aforementioned amount, and are supplied to respective ones of a set of circuits referred to as pulse position numerizing circuits, each of which obtains the position of the pulse signal, when the corresponding time point is reached. The clock signal generating circuit can be implemented as a circuit formed only of transistors, in particular, formed of CMOS inverters producing respectively predetermined amounts of delay.
With the above types of TAD A/D converters, it becomes possible to eliminate components such as operational amplifiers, capacitors, resistors, etc., that are required with a conventional type of A/D converter that must operate upon very small-amplitude analog signals. Hence, a TAD A/D converter can readily be implemented in integrated circuit form. In particular, such an A/D converter can be advantageously implemented by using CMOS integrated circuit technology.
At present, the design rule used in the manufacturing process for CMOS ICs is that the design rule in a transistor structure (i.e., minimum line width) is less than 100 nm, and sizes of 90 to 65 nm and even as small as 45 nm have been achieved. It is expected that such transistors will be made even smaller in future, and that it will soon be possible to achieve a design rule as small as 30 nm. Since TAD types of A/D converter employ only digital circuitry, they are especially suitable for being produced using such a leading-edge CMOS integrated circuit manufacturing process, with extremely small transistor sizes.
That is to say, since digital circuits perform only logical operations (AND, OR, etc.) and need only switch a signal between two levels, i.e., the “0” and “1” levels, it is not necessary to discriminate between small differences in signal level, such as a change from a “0.2” to a “0.35” level. As the size of the transistors used to constitute digital circuits is reduced, the effects of manufacturing defects (resulting in deviations of line widths from the design values) and effects of small dust particles adhering to the IC surface, will have a correspondingly greater adverse effect upon the operating characteristics of the transistors. In particular, deviations in line width that cause variations in the pattern areas of the gates of the transistors will result in differences between the respective drive capabilities of the transistors. However when the transistors constitute a digital circuit, whose input and output signals change only between the “0” and “1” levels, problems resulting from such manufacturing defects and dust, etc., are substantially avoided.
In particular, in the case of circuits produced using the latest CMOS IC manufacturing processes for micro-miniaturization, digital circuits will in general have a much greater tolerance for the effects of manufacturing defects than will analog circuits.
However when the design rule becomes extremely small, the effects of manufacturing defects and adhering dust particles cannot be ignored, even in the case of digital circuits, so that these effects will become of increasing importance in the future.
FIGS. 13A, 13B, 13C are respective explanatory diagrams, in which FIG. 13A is a pattern diagram of an inverter circuit formed of a P-channel FET (field effect transistor) and an N-channel FET formed in an IC chip, FIG. 13B is an expanded view of a P-channel FET in FIG. 13A, and FIG. 13C illustrates the effect of reducing the transistor width W and the transistor length L (i.e., the pattern width of the gate G) each by one half.
As illustrated in these diagrams, a portion of the pattern of a gate G such as gate Gp of the P-channel FET may be missing, due to manufacturing defects, so that the total effective area of that gate (i.e., the region enclosed by the drain D and source S of that transistor) is accordingly reduced. As can be readily understood from FIG. 13C, the smaller the transistor size (i.e., the smaller the transistor width W and transistor length L) the greater will become the effects of such manufacturing defects. This will have an adverse effect upon the transistor characteristics, and in particular upon the drive capability.
In order to achieve stable operation of a TAD type of A/D converter, it is necessary that the delay units of the pulse delay circuit produce respectively identical amounts of delay, so that the pulse signal will be transmitted along the successive delay units at a uniform speed during each measurement interval, as illustrated conceptually by the arrow lines in FIG. 14A. In FIG. 14A, for example, (K) corresponds to the time at which the pulse signal is outputted from the k-th delay unit, after successively traversing the first to k-th delay units.
However if there are small differences between the respective levels of drive capability of the transistors constituting the delay units, due to the effects of manufacturing defects and adhering dust particles, etc., then deviations will occur between the respective delay times of the delay units. This is conceptually illustrated in FIG. 14B, and it can be understood that this will result in deviations in the resolution of the A/D converted data. The resolution expresses the amount of change in level of the converter input voltage that will result in a corresponding change in the LSB (least significant bit) of the A/D converted data. It can be seen that this will result in the resolution varying in accordance with the level of the converter input signal, i.e., there will be large amounts of differential non-linearity.
In the case of the A/D converter of related document 2 above, it is necessary that each operation for detecting the position of the pulse signal within the pulse delay circuit, at the end of a measurement interval be performed while also correctly obtaining the count of total number of circulations from the circulation number counter This is necessary in order for the high-order bits (counter data) and low-order bits (pulse delay position data) of each A/D converted value to be matched. For that reason, a single timing signal is used to control latching of the circulation number counter data and pulse delay position.
The circulation number counter is generally a synchronous type of counter. As the number of bits constituting the count value is increased, the amount of load imposed on a clock signal supply line of the counter will increase accordingly. This increase in load results in a delay in operation of the circulation number counter, which results in problems.
The clock signal supplied to the circulation number counter is the output signal from a specific one of the delay units, in general, the final-stage delay unit. At a time point when the respective outputs of the delay units are latched to find the position reached by the pulse signal within the series of delay units, and the count value of the circulation number counter is also registered by a latch circuit, the aforementioned delay in operation of the circulation number counter may result in the count value being registered before it has been incremented by the most recent occurrence of outputting of the delayed pulse signal from the pulse delay circuit. In such a case, the high-order bits and low-order bits of the resultant A/D converted value will not correctly match, so that an accurate value will not be obtained.
Due to the above problem, it is necessary to insert a supply line drive buffer circuit for transferring the output from the final-stage delay unit to the circulation number counter. Accordingly, it is also necessary to insert a delay buffer circuit for supplying the latch timing signal to the counter latch circuit, in order to compensate for (i.e., balance) the delay introduced by the supply line drive buffer circuit.
However with increasing degrees of miniaturization of IC components, so that manufacturing defects and adhering dust particles result in greater deviations between the drive capabilities of respective transistors that constitute the delay buffer circuit and the supply line drive buffer circuit, it becomes increasingly difficult to achieve accurate matching of the respective amounts of delay that are introduced by these circuits. Hence, it becomes increasingly difficult to ensure that the high-order bits and low-order bits of each A/D converted value are correctly matched, so that accurate A/D converted data may not be obtainable.
In the case of the A/D converter of the related document 3 above, designating the delay time of a delay unit as Δt, it is necessary for the respective pulse position numerizing circuits to accurately use (in each A/D conversion operation) measurement intervals (sampling intervals) which respectively differ by a unit time amount Δt=Td/n, where Td is the amount of delay that is currently being produced by each of the delay units under the currently applied level of converter input voltage. As a result, it is necessary to generate sampling clock signals that are successively shifted in phase by the unit time interval Δt.
To generate such sampling clock signals, a total of n CMOS inverter circuits are utilized, each of which receives a reference clock signal, and the respective sizes of the transistors in the inverter circuits are adjusted such as to produce specific small differences in the switching voltage levels (and hence, in the signal level inversion timings) of the respective inverter circuits, such that the output signals from the inverter circuits will respectively differ in phase by the unit time amount Δt.
Hence, with such a clock signal generating circuit, if small differences occur between the respective drive capabilities of the transistors that constitute the clock signal generating circuit (i.e., due to the effects of manufacturing defects and adhering dust particles), it becomes impossible to accurately shift the phase by precise units of Δt. Thus, the resolution of A/D conversion will be lowered and the differential non-linearity will become large, since the A/D converted data are obtained by adding together the outputs from the respective pulse position numerizing circuits.